Signal Integrity Engineer

[Senior SI PI Engineer]

1.Qualifications:

a. Top expertise in signal integrity analysis with HFSS, SIwave, ADS, HyperLynx, Memory

Designer, COM analysis and Matlab scripts.

b. Top expertise in power integrity analysis with PowerDC, OptimizePI, PowerSI, or HSPICE.

c. Excellent communicator specifically interfacing with hyperscale data center customers.

d. Self-starter, self-motivated, self-actualized, and highly accountable with strong

communication skills

e. A good team player in working with customers as well as cross-functional teams.

f. Master's degree with 6 years SI PI work experience is a minimum, 10+ years work experience or PhD in signal integrity/power integrity is a plus.

g. Experienced in SI PI automation tool development with Python or PyAEDT is a plus.

h. Experienced in PNA/ENA measurement with micro-probing is a plus.

2. Responsibilities:

a. Signal integrity frequency domain and time domain analysis for 56G/112G PAM4 and

above including IL, RL, crosstalk, TDR impedance, eye diagram, BER, COM, ERL, VEC, VEO,

ILD, ICN on overall PCB channels with ASIC models including TX FIR , RX CTLE, DFE, FFE at a

system level.

b. PI DC analysis, power/ground planes design, pre-layout floor planning, post-layout

optimization, and troubleshooting.

c. PI AC impedance analysis, PDN decoupling capacitors design, optimization, analog power

filtering for ASICs, transient analysis including CPM, and troubleshooting.

d. All SI/PI aspects of high-speed serial channels and DDRx SI analysis such as ASIC

breakouts/fanouts, connectors, cables, including crosstalk, reflections, setup and hold

timings, and other issues including understanding of PCB fabrication rules and tolerances.

e. All aspects of high-speed serial channel link training, including thorough understanding of

the applicable standard. This would involve working closely with the ASIC vendor to help

them understand Accton's design and channel models.