Lvds Jobs

Mixed Signal Analog Circuit Designer (RDSS Intern)

Permanent Job

Hsinchu ,

Taiwan

0-2 years

analog circuit layout concepts analog circuit simulation tools digital links IO pads XA design and verification tools Cadence custom circuit design tools Skill DVI submicron CMOS technologies DRC high-speed serial links Finesim LVDS HDMI PLL techniques Cadence"s IC design environment virtuoso LVS low-jitter clock synthesis Display Port Hspice ADC display interfaces MIPI PHY Usb perl python Scripting Languages

11 days ago

Senior FPGA Engineer (Malaysia based)

Permanent Job

Taiwan

2-4 years

LPC Uvm Intel Rtl Design assertion based verification Quartuse-II MDIO Modelsim functional coverage techniques project management Communications Skills multi-tasking Problem Solving lattice Vivado LVDS English Speaking Xilinx Fpga Spi DDR Pcie Verilog Debugging I2c Ise System Verilog Uart Ethernet

5 months ago

Home

lvds Jobs

Top Industry

Lvds Jobs

Mixed Signal Analog Circuit Designer (RDSS Intern)

Senior FPGA Engineer (Malaysia based)