Verilog Jobs

Staff Applications Engineer - Compute Subsystems

Permanent Job

Hsinchu ,

Taiwan

8-10 years

HDLs CPU architecture principles ASIC/SoC design processes CCIX AMBA bus protocols ASIC VHDL SoC design principles CXL System-Verilog arm architecture python Perl Pcie Verilog Scripting Languages

5 days ago

Principal Engineer, ASIC Development Engineering

Permanent Job

Taiwan

3-5 years

RISC microprocessors Problem Solving Skills structured methodologies digital scope Arc storage interface bus analyzer JTAG-based debuggers digital hardware design Embedded Firmware Storage Systems Perl Verilog C Programming Arm Python

12 days ago

Mixed Signal Design Engineer (RDSS Intern)

Permanent Job

Taiwan

0-2 years

Mixed-Signal CMOS FinFET High Speed Memory Hspice XA Spectre Device Reliability Cadence Custom Design Tools NanoTime Circuit Design Esd Latch-Up FineSim Lab Test and Measurement Equipment Io Verilog Matlab Analog

9 days ago

MTS Logic Design

Permanent Job

Taiwan ,

Taipei City

2-5 years

ASIC Synthesis cdc quartus ASIC RDC Vivado Linting UPF Fpga Verilog System Verilog

18 days ago

SPE Logic Design

Permanent Job

Taiwan ,

Taipei City

10-12 years

ASIC Synthesis cdc Linting UPF quartus ASIC RDC Vivado CXL Fpga Pcie Verilog System Verilog

22 days ago

Mixed Signal Design Engineer (RDSS Intern)

Permanent Job

Hsinchu ,

Taiwan

0-2 years

Mixed-Signal Digital Circuits High-Speed Memory IO Circuit Design CMOS FinFET Analytical Skills Verilog-A Hspice XA Spectre Cadence Interpersonal Skills teammate FineSim Verilog Matlab Debugging Analog

24 days ago

Mixed Signal Circuit Designer Intern

Permanent Job

Hsinchu ,

Taiwan

0-2 years

Mixed-Signal Analytical Skills Hspice XA Spectre CMOS Cadence Interpersonal Skills Circuit Design behavioral modeling teammate High-Speed FineSim SERDES FinFET Io Verilog Matlab Debugging Analog

24 days ago

ASIC Design Engineer (Image Multimedia Direction)

Permanent Job

Beijing ,

China

3-5 years

NIC systemverilog Ip DP SVA MIPI Axi SDC SERDES Verilog Fpga Eda Noc Tcl Python Perl EDP

26 days ago

ASIC Design Engineer (Image Multimedia Direction)

Permanent Job

Shanghai ,

China

3-5 years

NIC systemverilog Ip DP SVA MIPI Axi SDC SERDES Verilog Fpga Eda Noc Tcl Python Perl EDP

26 days ago

Serdes IP Applications Engineer

Permanent Job

Hsinchu ,

Taiwan

3-5 years

physical implementation Synthesis silicon debug static timing check Simulation PCI Express gate-level simulation equivalence check RTL Coding CXL Ethernet Protocols Verilog

22 days ago

Semiconductor Custom IC Circuit Designer

Permanent Job

Taiwan

4-6 years

Memory Circuit Debug Business Simulation clock silicon cross functional Schematic CMOS Layout Design Optimization Spice transistor communication Verilog

a month ago

CAD Tools Development Engineer - Hardware (RDSS Intern)

Permanent Job

Taiwan

0-2 years

Design for Testing logic cells ATPG bist Scan CAD software developments ASIC design principles C++ Tcl Verilog Jtag Python Perl Algorithms

a month ago

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Permanent Job

Hsinchu ,

Taiwan

Fresher

VHDL Ip Fpga C++ Verilog MATLAB Tcl

5 months ago

Senior FPGA Engineer (Malaysia based)

Permanent Job

Taiwan

2-4 years

LPC Uvm Intel Rtl Design assertion based verification Quartuse-II MDIO Modelsim functional coverage techniques project management Communications Skills multi-tasking Problem Solving lattice Vivado LVDS English Speaking Xilinx Fpga Spi DDR Pcie Verilog Debugging I2c Ise System Verilog Uart Ethernet

5 months ago