Responsibilities
1. Participate in the collection and decomposition of chip multimedia direction (including ISP/Display/media high-speed interface/NPU) requirements, participate in specification formulation, and be able to provide corresponding system solutions 2. Be responsible for the implementation and system integration of multimedia algorithm IP, and output corresponding documents and codes 3. Be responsible for the design of multimedia subsystems or local micro-architectures, and be able to complete PPA evaluation 4. Deeply participate in the entire chip design process, optimize the PPA indicators in the multimedia field, and meet the delivery standards of each stage.
Qualifications
1. Bachelor degree or above, more than 3 years of R&D work experience 2. Familiar with digital circuit design process, proficient in Verilog/SystemVerilog/SVA and other languages 3. Proficient in front-end design related EDA tools (VCS/Verdi/Lint/CDC, etc.) 4. Familiar with advanced process technology, low-power digital circuit design and verification process 5. Familiar with Perl/Python/Tcl and other scripting language development 6. Have good learning ability, be proactive and responsible. Those with the following experience are preferred: 1. Have experience in image cache, compression algorithm and AI accelerator development 2. Familiar with AXI bus performance analysis, Noc/NIC integration experience 3. Familiar with DP/EDP/MIPI and other related interface protocols, and have a certain understanding of the electrical characteristics of high-speed Serdes 4. Have SDC development capabilities and static timing analysis experience 5. Have FPGA programming and IP prototyping experience.
